IC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier without too much penalty regarding area while keeping the gain-bandwidth unaffected in the same time? Moderate inversion yields high gains, but the concomitant area increase adds parasitics that restrict bandwidth. Which methodology to use in order to come across the best compromise(s)? Is synthesis a mixture of design experience combined with cut and tries or is it a constrained multivariate optimization problem, or a mixture? Optimization algorithms are attractive from a system perspective of course, but what about low-voltage low-power circuits, requiring a more physical approach? The connections amid transistor physics and circuits are intricate and their interactions not always easy to describe in terms of existing software packages. The gm/ID synthesis methodology is adapted to CMOS analog circuits for the transconductance over drain current ratio combines most of the ingredients needed in order to determine transistors sizes and DC currents.

Dr. Paul Jespers is Professor Emeritus at UCL, Louvain-la-Neuf, Belgium, and has been visiting professor at Stanford ('67-'69) and UC Berkeley ('90-'91). He has coauthored several books, and in 2001 published "Integrated DigitaltoAnalog and AnalogtoDigital Converters" which was published by Wiley (ISBN 0198564465)

Preface. Notations. 1. Sizing the Intrinsic Gain Stage. 1.1 The intrinsic Gain Stage. 1.2 The I.G.S frequency response. 1.3 Sizing the I.G.S. 1.4 The gm/ID sizing methodology. 1.5 Conclusions. 2. The Charge Sheet Model revisited. 2.1 Why the Charge Sheet Model? 2.2 The generic drain current equation. 2.3 The C.S.M drain current equation. 2.4 Common source characteristics. 2.5 Weak inversion approximation. 2.6 The gm/ID ratio in the common source configuration. 2.7 Common gate characteristic of the Saturated Transistor. 2.8 A few concluding remarks concerning the C.S.M. 3. Graphical interpretation of the Charge Sheet Model. 3.1 A graphical representation of ID. 3.2 More on the VT curve. 3.3 Two approximate representations of VT. 3.4 A few examples illustrating the use of the graphical construction. 3.5 A closer look to the pinch-off region. 3.6 Conclusions. 4. Compact modeling. 4.1 The basic compact model. 4.2 The E.K.V model. 4.3 The common source characteristics ID(VG). 4.4 Strong and weak inversion asymptotic approximations derived from the compact model. 4.5 Checking the compact model against the C.S.M. 4.6 Evaluation of gm/ID. 4.7 Sizing the Intrinsic Gain Stage by means of the E.K.V. model. 4.8 The common gate gms/ID ratio. 4.9 An earlier compact model. 4.10 Modelling mobility degradation. 4.11 Conclusions. 5. The real transistor. 5.1 Short channel effects. 5.2 Checking the assumption by means of a¿¿experimental¿ evidence. 5.3 Compact model parameters versus bias and gate length. 5.4 Reconstructing ID(VDS) characteristics. 5.5 Evaluation of gx/ID ratios. 5.6 Conclusions. 6. The real Intrinsic Gain Stage. 6.1 The dependence on bias conditions of the gm/ID and gd/ID ratios. 6.2 Sizing the I.G.S with semi-empirical data. 6.3 Model driven sizing of the I.G.S. 6.4 Slew-rate considerations. 6.5 Conclusions. 7. The common gate configuration. 7.1 Drain current versus source-to-substrate voltage. 7.2 The cascoded Intrinsic Gain Stage. 8. Sizing the Miller Op. Amp. 8.1 Introductary considerations. 8.2 The Miller Op. Amp. 8.3 Sizing the Miller Operational Amplifier. 8.4 Conclusion. Annex 1. How to utilize the C.D. ROM data. Annex 2. The MATLAB toolbox. Annex 3. Temperature and Mismatch, fromC.S.M. to E.K.V. Annex 4. E.K.V. intrinsic capacitance models. Bibliography. Index.